XC2C128-7VQ100C
Produktnummer:
12970
Hersteller:
Xilinx
Lagerbestand:
360
VPE:
90
Date Code:
04+
Verpackung:
Tray
Bauform:
VQFP-100
RoHs Status:
no
| Anzahl | Stückpreis |
|---|---|
| Bis 90 |
7,50 €*
|
| Bis 180 |
7,30 €*
7,50 €*
(2.67% gespart)
|
| Bis 360 |
7,00 €*
7,50 €*
(6.67% gespart)
|
| Ab 361 |
6,50 €*
7,50 €*
(13.33% gespart)
|
Mindestbestellwert: 50,00 EUR
Produktinformationen "XC2C128-7VQ100C"
CoolRunner-II CPLD
• Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 ?A quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
Datenblatt: XC2C128.pdf
• Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 ?A quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
Datenblatt: XC2C128.pdf