EPM7096LC68-7
Produktnummer:
13512
Hersteller:
Altera
Lagerbestand:
0
VPE:
18
Date Code:
2005+
Verpackung:
Tube
Bauform:
PLCC-68
RoHs Status:
no
| Anzahl | Stückpreis |
|---|---|
| Bis 20 |
25,00 €*
|
| Bis 40 |
23,00 €*
25,00 €*
(8% gespart)
|
| Ab 41 |
20,00 €*
25,00 €*
(20% gespart)
|
Nicht mehr verfügbar
Mindestbestellwert: 50,00 EUR
Produktinformationen "EPM7096LC68-7"
High Density, erasable CMOS EPLD
- High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
- 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
- Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
- Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
- 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
- PCI-compliant devices available
Datenblatt: EPM7096.pdf
- High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
- 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
- Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
- Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
- 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
- PCI-compliant devices available
Datenblatt: EPM7096.pdf