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Xicor
X2210AP
Beschreibung: 64 x 4 Bit Nonvolatile Static RAM Datenblatt: X2210.pdf

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1 .50*
Xicor
X2402PI
Beschreibung: 2K (256 x 8-Bit) serial E2PROM Datenblatt: X2402P.pdf

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1 .00*
Xicor
X24C02S8T1
Beschreibung: Serial E2PROM Datenblatt: X24C02.pdf

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0 .50*
Xicor
X24C04S8
Beschreibung: 4K Serial E2PROM Datenblatt: X24C04.pdf

2 .00*
Xicor
X25043SI
Beschreibung: 4K (512 x 8-Bit) programmable watchdog supervisory 5 Volt E2PROM Datenblatt: X25043.pdf

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1 .75*
Xicor
X25043SI
Beschreibung: 4K (512 x 8-Bit) programmable watchdog supervisory 5 Volt E2PROM Datenblatt: X25043.pdf

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1 .20*
Xicor
X25F064S
Beschreibung: 64K SerialFlash™ Memory With Block LockTM Protection Datenblatt: X25F064.pdf

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0 .75*
Xicor
X2816AP
Beschreibung: 16K (2048 x 8 Bit) 5 Volt, Byte Alterable E2PROM

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3 .00*
Xicor
X2816CJI-20
Beschreibung: 5 Volt, Byte Alterable E2PROM Datenblatt: X2816C.pdf

11 .50*
Xicor
X2864AP-35
Beschreibung: Parallel Electrically-Erasable PROM (EEPROM) - With CE/WE/OE Number of Words=8k Bits Per Word=8 t(a) Max. (s) Access Time=350n Output Config=3-State Number of Chip Selects=1 Program Voltage (V)=5.0 Nom. Supp (V)=5.0

5 .00*
Xicor
X5043S8
Beschreibung: CPU Supervisor with 4K SPI EEPROM Datenblatt: X5043S8.pdf

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1 .10*
Xicor
X9241WS
Beschreibung: Quad E2POT™ Nonvolatile Digital Potentiometer Datenblatt: X9241.pdf

6 .00*
Xicor
X9C103S
Beschreibung: Digitally Controlled Potentiometer Datenblatt: X9C103S.pdf

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1 .75*
Xicor
X9C303V8T2
Digitally Controlled Potentiometer (XDCP™) Datenblatt: X9C303.pdf

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1 .00*
Texas Instruments
XAM3359ZCZ
Sitara Processor: ARM Cortex-A8, EtherCAT, 3D, PRU-ICSS Core: ARM Cortex A8 Number of Cores: 1 Core Data Bus Width: 32 bit L1 Cache Instruction Memory: 32 kB L1 Cache Data Memory: 32 kB Memory Type: L1/L2/L3 Cache, RAM, ROM Data RAM Size: 64 kB Data ROM Size: 176 kB Interface Type: CAN, Ethernet, I2C, SPI, UART, USB I/O Voltage: 1.8 V, 3.3 V L2 Cache Instruction / Data Memory: 256 kB Number of Timers/Counters: 8 x 32 bit Processor Series: Sitara Datenblatt: XAM3359ZCZ.pdf

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23 .00*
Xilinx
XC17256DPC
QPRO Family of XC1700D QML Configuration PROM Datenblatt: XC17256D.pdf

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2 .09*
Xilinx
XC1736A
Beschreibung: One Time Programmable Serial Configuration PROM Datenblatt: XC1736.pdf

2 .30*
Xilinx
XC17S50LPC
Beschreibung: Spartan/XL Family One-Time Programmable Configuration PROMs Datenblatt: XC17S50.pdf

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2 .30*
Xilinx
XC18V02VQ44C
XC18V00 Series In-System-Programmable Configuration PROMs - In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs - Endurance of 20,000 Program/Erase Cycles - Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C) - IEEE Std 1149.1 Boundary-Scan (JTAG) Support - JTAG Command Initiation of Standard FPGA Configuration - Simple Interface to the FPGA - Cascadable for Storing Longer or Multiple Bitstreams - Low-Power Advanced CMOS FLASH Process - Dual Configuration Modes - Serial Slow/Fast Configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) - 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals - 3.3V or 2.5V Output Capability - Design Support Using the Xilinx ISE™ Foundation™ Datenblatt: XC18V04VQG44C.pdf

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20 .00*
Xilinx
XC18V04VQG44C
XC18V00 Series In-System-Programmable Configuration PROMs - In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs - Endurance of 20,000 Program/Erase Cycles - Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C) - IEEE Std 1149.1 Boundary-Scan (JTAG) Support - JTAG Command Initiation of Standard FPGA Configuration - Simple Interface to the FPGA - Cascadable for Storing Longer or Multiple Bitstreams - Low-Power Advanced CMOS FLASH Process - Dual Configuration Modes - Serial Slow/Fast Configuration (up to 33 MHz) - Parallel (up to 264 Mb/s at 33 MHz) - 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals - 3.3V or 2.5V Output Capability - Design Support Using the Xilinx ISE™ Foundation™ - Lead-Free (Pb-Free) Packaging Datenblatt: XC18V04VQG44C.pdf

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42 .00*
Xilinx
XC2C128-7VQ100C
CoolRunner-II CPLD • Optimized for 1.8V systems - As fast as 5.7 ns pin-to-pin delays - As low as 13 ?A quiescent current • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V • Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management · DataGATE enable (DGE) signal control - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes · Optional DualEDGE triggered registers · Clock divider (divide by 2,4,6,8,10,12,14,16) · CoolCLOCK - Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables · Global set/reset - Advanced design security Datenblatt: XC2C128.pdf

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6 .50*
Xilinx
XC2S200-5FG256C
Spartan-II 2.5V FPGA Automotive IQ Product Family - Guaranteed to meet full electrical specifications over TJ = –40°C to +125°C - Second generation ASIC replacement technology - Densities as high as 5,292 logic cells with up to 200,000 system gates - Streamlined features based on Virtex architecture - Unlimited reprogrammability - SelectRAM+™ hierarchical memory: - 16 bits/LUT distributed RAM - Configurable 4K-bit block RAM - Fast interfaces to external RAM - Fully PCI compliant - Low-power segmented routing architecture - Full readback ability for verification/observability - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic - Family footprint compatibility in common packages - 16 high-performance interface standards - Zero hold time simplifies system timing - Fully supported by powerful Xilinx development system - Foundation™ ISE Series: Fully integrated software - Alliance Series™: For use with third-party tools - Fully automatic mapping, placement, and routing Datenblatt: XC2S200.pdf

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27 .00*
Xilinx
XC2S200-5PQ208I
Spartan-II 2.5V FPGA Automotive IQ Product Family - Guaranteed to meet full electrical specifications over TJ = –40°C to +125°C - Second generation ASIC replacement technology - Densities as high as 5,292 logic cells with up to 200,000 system gates - Streamlined features based on Virtex architecture - Unlimited reprogrammability - SelectRAM+™ hierarchical memory: - 16 bits/LUT distributed RAM - Configurable 4K-bit block RAM - Fast interfaces to external RAM - Fully PCI compliant - Low-power segmented routing architecture - Full readback ability for verification/observability - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic - Family footprint compatibility in common packages - 16 high-performance interface standards - Zero hold time simplifies system timing - Fully supported by powerful Xilinx development system - Foundation™ ISE Series: Fully integrated software - Alliance Series™: For use with third-party tools - Fully automatic mapping, placement, and routing Datenblatt: XC2S200.pdf

25 .00*
Xilinx
XC2S400E-6FT256C
Spartan-IIE FPGA Family - Densities as high as 15,552 logic cells with up to 600,000 system gates - Streamlined features based on Virtex®-E FPGA architecture - Unlimited in-system reprogrammability - Very low cost - Cost-effective 0.15 micron technology - Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant - Low-power segmented routing architecture - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control - Eliminate clock distribution delay - Multiply, divide, or phase shift - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Datenblatt: XC2S400E.pdf

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100 .00*
Xilinx
XC2VP40-6FF1152C
Beschreibung: Virtex-ii Pro Field Programmable Gate Array Datenblatt: XC2VP40.pdf

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500 .00*
Xilinx
XC3020-70PC68C
Beschreibung: Field Programmable Gate Arrays Datenblatt: XC3020.pdf

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6 .50*
Xilinx
XC3S200A-4FTG256C
Beschreibung: Spartan-3A FPGA Datenblatt: XC3S200A.pdf

14 .00*
Xilinx
XC3S400-4FT256C-ESA
Spartan-3 FPGA Datenblatt: XC3S400.pdf

10 .00*
Xilinx
XC3S500E-4PQG208I
FPGA - Field Programmable Number of Logic Elements: 10476 LE Number of I/Os: 158 I/O Supply Voltage - Min: 1.14 V Supply Voltage - Max: 1.26 V Distributed RAM: 73 kbit Embedded Block RAM - EBR: 360 kbit Maximum Operating Frequency: 300 MHz Number of Gates: 500000 Minimum Operating Temperature: - 40 C Maximum Operating Temperature: + 100 C Datenblatt: XC3S500E.pdf

112 .50*
Xilinx
XC3SD3400A-4CSG484I
Spartan-3A DSP FPGA - Very low cost, high-performance DSP solution for high-volume, cost-conscious applications - 250 MHz XtremeDSP DSP48A Slices - Dedicated 18-bit by 18-bit multiplier - Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade - 48-bit accumulator for multiply-accumulate (MAC) operation - Integrated adder for complex multiply or multiply-add operation - Integrated 18-bit pre-adder - Optional cascaded Multiply or MAC - Re-programmability Support Yes - Maximum Internal Frequency 667 MHz - Device Logic Cells 53712 - Screening Level Industrial - Maximum Operating Supply Voltage 1.26 V - Maximum Number of User I/Os 309 - Device Logic Gates 3400000 - Minimum Operating Supply Voltage 1.14 V - Operating Temperature -40 to 100 °C - Fabrication Technology 90nm Datenblatt: XC3SD3400A.pdf

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80 .00*
Xilinx
XC4003A-6PQ100C
Beschreibung: Logic Cell Array Datenblatt: XC4003.pdf

30 .00*
Xilinx
XC4008-5PC84C
Beschreibung: Third Generation Field-Programmable Gate Arrays Datenblatt: XC4008.pdf

50 .00*
Xilinx
XC4010E-4BG225C
Beschreibung: Field Programmable Gate Array Datenblatt: XC4010E.pdf

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50 .00*
Xilinx
XC4013-4PQ208C
Field-Programmable Gate Arrays Datenblatt: XC4013.pdf

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25 .00*
Xilinx
XC4013XL-3PQ208C
Field-Programmable Gate Arrays Number of LABs/CLBs: 576 Number of Logic Elements/Cells: 1368 Total RAM Bits: 18432 Number of I/O: 160 Number of Gates: 13000 Voltage - Supply: 3V to 3.6V Operating Temperature: 0°C to 85°C (TJ) Datenblatt: XC4013XL.pdf

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37 .10*
Xilinx
XC4020XLA-09PQ208I
Field Programmable Gate Arrays Supply Voltage: 3.0V - 3.6V Logic Cells: 1862 CLB Matrix: 28 x 28 Maximum I/O Accessible per Package: 160 Datenblatt: XC4020XLA.pdf

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37 .50*
Xilinx
XC4028XLA-09BG256C
Field Programmable Gate Array Datenblatt: XC4028XLA.pdf

40 .00*
Xilinx
XC5210-6PC84C
Beschreibung: Field Programmable Gate Array Datenblatt: XC5210.pdf

20 .00*
Motorola
XC56156FE60
16bit General Purpose Digital Signal Processor — Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz — Up to 180 Million Operations Per Second (MOPS) at 60 MHz — Highly parallel instruction set with unique DSP addressing modes — Two 40-bit accumulators including extension byte — Parallel 16 ´ 16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) — Double precision 32 ´ 32-bit multiply with 72-bit result in 6 instruction cycles — Least Mean Square (LMS) adaptive loop filter in 2 instructions — 40-bit Addition/Subtraction in 1 instruction cycle — Fractional and integer arithmetic with support for multiprecision arithmetic — Hardware support for block-floating point FFT — Hardware-nested DO loops including infinite loops — Zero-overhead fast interrupts (2 instruction cycles) — Three 16-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip

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6 .00*
Torex Semiconductor Ltd.
XC62AP5002PR
Beschreibung: LDO voltage regulator

Ab
0 .10*