MP...

MP Micro Power Systems Inc.

MP7528JN

Beschreibung: CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter Datenblatt: MP7528.pdf

€ 7 .00*

Freescale Semiconductor

MPC8280VVUPEA

Microprocessors - MPU 450 MHz 885 MIPS Core: 603e Number of Cores: 1 Core Data Bus Width: 32 bit Maximum Clock Frequency: 450 MHz L1 Cache Instruction Memory: 16 kB L1 Cache Data Memory: 16 kB Operating Supply Voltage: 1.45 V to 1.6 V I/O Voltage: 3.3 V Instruction Type: Floating Point Memory Type: L1 Cache Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 105 C

€ 301 .30*

Freescale Semiconductor

MPC8343EZQAGD

Beschreibung: PowerQUICC II Pro Integrated Host Processor Datenblatt: MPC8343E.pdf

€ 20 .00*

Freescale Semiconductor

MPC8358EVRAGDGA

PowerQUICC II Pro Processor - Operates at up to 400 MHz (for the MPC8358E) - High-performance, superscalar processor core - Floating-point, integer, load/store, system register, and branch processing units - 32-Kbyte instruction cache, 32-Kbyte data cache - Lockable portion of L1 cache - Dynamic power management - Software-compatible with the Freescale processor families implementing the Power Architecture™ technology - Two 32-bit RISC controllers for flexible support of the communications peripherals, each operating up to 400 MHz (for the MPC8358E) - Serial DMA channel for receive and transmit on all serial channels - QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™) Datenblatt: MPC8358E.pdf

€ 30 .00*

Freescale Semiconductor

MPC8548ECVTAUJB

MPU PowerQUICC III Integrated Processor High-performance 32-bit core built on Power Architecture® technology. — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte to 4-Gbyte page sizes. — Enhanced hardware and software debug support Datenblatt: MPC8548E.pdf

€ 150 .00*