CPLD - One-Time-Programmable Logic Device - 48 Macrocells
Program Memory Type: EPROM
Number of Global Clocks: 2
Number of Macro Cells: 48
Product Terms: 8
Device System Gates: 900
Data Gate: No
Maximum Number of User I/Os: 64
In-System Programmability: No
Programmability: Yes
Reprogrammability Support: Yes
Maximum Internal Frequency (MHz): 41.67
Maximum Clock to Output Delay (ns): 20
Maximum Propagation Delay Time (ns): 35
Speed Grade: 35
Individual Output Enable Control: No
Minimum Operating Supply Voltage (V): 4.75
Maximum Operating Supply Voltage (V): 5.25
Typical Operating Supply Voltage (V): 5
Minimum Operating Temperature (°C): 0
Maximum Operating Temperature (°C): 70
FPGA - Field Programmable Gate Array
Number of Logic Elements: 12060 LE
Number of I/Os: 249 I/O
Supply Voltage - Min: 1.5 V
Supply Voltage - Max: 3.3 V
Maximum Operating Frequency: 250 MHz
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Datenblatt:
EP1C12F324C8N.pdf
Programmable Logic Device ACEX 1K Family
- Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array block (EAB)
– Logic array for general logic functions
- High density
– 10,000 to 100,000 typical gates
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity
- Cost-efficient programmable architecture for high-volume applications
– Cost-optimized process
– Low cost solution for high-performance communications applications
- System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Datenblatt:
EP1K100QC208-3N.pdf
FPGA - Field Programmable Gate Array
Embedded Memory: 117 kbit
Number of I/Os: 89 I/O
otal Memory: 119808 bit
Maximum Operating Frequency: 260 MHz
Operating Supply Voltage: 1.15 V to 1.25 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Flex 10K Device Family - Embedded - FPGAs (Field Programmable Gate Array)
Number of LABs/CLBs: 360
Number of Logic Elements/Cells: 2880
Total RAM Bits: 20480
Number of I/O: 246
Number of Gates: 116000
Voltage - Supply: 4.75V to 5.25V
Mounting Type: Surface Mount
Operating Temperature: 0C to 70C (TA)
Datenblatt:
EPF10K50BC356.pdf
CPLD - Complex Programmable Logic
Operating Supply Voltage: 3.3 V
Number of Macrocells: 64 Macrocell
Number of I/Os: 34 I/O
Supply Voltage - Max: 3.6 V
Supply Voltage - Min: 3 V
Maximum Operating Frequency: 222.2 MHz
Propagation Delay - Max: 4.5 ns
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
CPLD - Complex Programmable Logic
Number of Macrocells: 64
Number of Gates: 1250
Number of Logic Array Blocks - LABs: 4
Maximum Operating Frequency: 151.5 MHz
Propagation Delay - Max: 6 ns
Number of I/Os: 36 I/O
Operating Supply Voltage: 5 V
Supply Voltage - Max: 3.6 V
Supply Voltage - Min: 3 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Datenblatt:
EPM7064.pdf
Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins
Number of Macrocells: 64
Number of Gates: 1250
Number of Logic Array Blocks - LABs: 4
Maximum Operating Frequency: 151.5 MHz
Propagation Delay - Max: 6 ns
Number of I/Os: 36 I/O
Operating Supply Voltage: 5 V
Supply Voltage - Max: 3.6 V
Supply Voltage - Min: 3 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Datenblatt:
EPM7064.pdf
High Density, erasable CMOS EPLD
- High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
- 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
- Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
- Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
- 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
- PCI-compliant devices available
Datenblatt:
EPM7096.pdf
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000
Family Name: MAX® 7000S
Program Memory Type: EEPROM
Number of Logic Blocks/Elements: 8
Number of Global Clocks: 2
Number of Macro Cells: 128
Product Terms: 32
Device System Gates: 2500
Data Gate: No
Maximum Number of User I/Os: 84
In-System Programmability: Yes
Programmability: Yes
Reprogrammability Support: Yes
Maximum Internal Frequency (MHz): 100
Maximum Clock to Output Delay (ns): 8
Maximum Propagation Delay Time (ns): 15
Speed Grade: 15
Individual Output Enable Control: Yes
Minimum Operating Supply Voltage (V): 4.75
Maximum Operating Supply Voltage (V): 5.25
Typical Operating Supply Voltage (V): 5
I/O Voltage (V): 3.3 / 5
Minimum Operating Temperature (°C): 0
Maximum Operating Temperature (°C): 70
Supplier Temperature Grade: Commercial
Datenblatt:
EPM7128S.pdf
Ab
€11.00*
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