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Altera
EP1810LC-35T
CPLD - One-Time-Programmable Logic Device - 48 Macrocells Program Memory Type: EPROM Number of Global Clocks: 2 Number of Macro Cells: 48 Product Terms: 8 Device System Gates: 900 Data Gate: No Maximum Number of User I/Os: 64 In-System Programmability: No Programmability: Yes Reprogrammability Support: Yes Maximum Internal Frequency (MHz): 41.67 Maximum Clock to Output Delay (ns): 20 Maximum Propagation Delay Time (ns): 35 Speed Grade: 35 Individual Output Enable Control: No Minimum Operating Supply Voltage (V): 4.75 Maximum Operating Supply Voltage (V): 5.25 Typical Operating Supply Voltage (V): 5 Minimum Operating Temperature (°C): 0 Maximum Operating Temperature (°C): 70

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15 .00*
Altera
EP1C12F324C8N
FPGA - Field Programmable Gate Array Number of Logic Elements: 12060 LE Number of I/Os: 249 I/O Supply Voltage - Min: 1.5 V Supply Voltage - Max: 3.3 V Maximum Operating Frequency: 250 MHz Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 70 C Datenblatt: EP1C12F324C8N.pdf

120 .00*
Altera
EP1K100QC208-3N
Programmable Logic Device ACEX 1K Family - Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array block (EAB) – Logic array for general logic functions - High density – 10,000 to 100,000 typical gates – Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity - Cost-efficient programmable architecture for high-volume applications – Cost-optimized process – Low cost solution for high-performance communications applications - System-level features – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices – Low power consumption – Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz – Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz Datenblatt: EP1K100QC208-3N.pdf

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30 .00*
Altera
EP1K10TC144-3N
Programmable Logic Device ACEX 1K Family Datenblatt: EP1K10TC144.pdf

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10 .00*
Altera
EP1S30F780I6N
Beschreibung: FPGA - Field Programmable Gate Array, Stratix I Datenblatt: EP1S30F780I6N.pdf

1000 .00*
Altera
EP2C20F256I8N
Cyclone II FPGA, 18752 Cells, 402.58MHz, 90nm Technology, 1.2V Datenblatt: EP2C20F256I8N.pdf

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58 .00*
Altera
EP2C5T144C8N
FPGA - Field Programmable Gate Array Embedded Memory: 117 kbit Number of I/Os: 89 I/O otal Memory: 119808 bit Maximum Operating Frequency: 260 MHz Operating Supply Voltage: 1.15 V to 1.25 V Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 70 C

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14 .67*
Altera
EP310DM
Beschreibung: UV-Erasable Programmable Logic Device (EPLD) - Prgrmble Outputs

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9 .00*
Altera
EP312LI-30
Beschreibung: High-Performance EPLD With 12 Macrocells Datenblatt: EP312.pdf

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3 .00*
Altera
EP4SGX70HF35C4N
FPGA - Field Programmable Gate Array FPGA - Stratix IV GX 2904 LABs 488 IOs - Product: Stratix IV GX - Number of Logic Elements: 72600 - Number of Logic Array Blocks - LABs: 2904 - Number of I/Os: 488 I/O - Operating Supply Voltage: 900 mV - Minimum Operating Temperature: 0 C - Maximum Operating Temperature: + 70 C - Mounting Style: SMD/SMT - Data Rate: 600 Mb/s to 8.5 Gb/s - Maximum Operating Frequency: 600 MHz Datenblatt: EP4SGX70.pdf

650 .00*
PCA Electronics Inc.
EP8202-HL
Beschreibung: Low Profile TTL Compatible Active Delay Line Datenblatt: EP8202.pdf

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1 .10*
Altera
EP910ILC-15
Beschreibung: CPLD, EP910 Family, ECMOS Process, 450 Gates, 24 Macro Cells, 24 Reg., 24 User I/Os, 5V Supply, 30 Speed Grade Datenblatt: EP910LC.pdf

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9 .00*
Altera
EPC4QC100N
Beschreibung: 4MBIT, 66,7MHz, FPGA, Configuration Device Datenblatt: EPC4QC100N.pdf

20 .00*
Altera
EPCS4SI8N
Beschreibung: Serial Configuration (EPCS) Devices Datenblatt: EPCS4SI8N.pdf

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7 .00*
Altera
EPCS64SI16N
Serial Configuration (EPCS) Devices Configuration Memory IC - Memory Type: Flash - Memory Size: 64 Mbit - Maximum Operating Frequency: 40 MHz - Operating Supply Voltage: 3.3 V - Minimum Operating Temperature: - 40 C - Maximum Operating Temperature: + 85 C Datenblatt: EPCS64.pdf

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18 .00*
Altera
EPF10K10LC84-3
FPGA - Field Programmable Gate Array, Flex 10K Device Family Datenblatt: EPF10K10LC84-3.pdf

40 .00*
Altera
EPF10K10QC208-3
FPGA - Field Programmable Gate Array, Flex 10K Device Family Datenblatt: EPF10K10QC208.pdf

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10 .45*
Altera
EPF10K20RC208-3
Flex 10K Device Family Die IC´s weisen etwas Korrosion an den Pin`s auf, daher ist nur Handlötung möglich. Datenblatt: EPF10K10QC208.pdf

Varianten ab 18,00 €*
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19 .60*
Altera
EPF10K30AQC208-1
Beschreibung: Flex 10K Device Family Datenblatt: EPF10K10QC208.pdf

100 .00*
Altera
EPF10K50BC356-3
Flex 10K Device Family - Embedded - FPGAs (Field Programmable Gate Array) Number of LABs/CLBs: 360 Number of Logic Elements/Cells: 2880 Total RAM Bits: 20480 Number of I/O: 246 Number of Gates: 116000 Voltage - Supply: 4.75V to 5.25V Mounting Type: Surface Mount Operating Temperature: 0C to 70C (TA) Datenblatt: EPF10K50BC356.pdf

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50 .00*
Altera
EPF10K50SFC484-1X
Beschreibung: Flex 10K Device Family Datenblatt: EPF10K50.pdf

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175 .00*
Altera
EPF6016BC256-3
Beschreibung: Programmable Logic Device Datenblatt: EPF6016.pdf

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20 .00*
Altera
EPF8636AQC208-4
Beschreibung: Low-cost, high-density, register-rich CMOS programmable logic device (PLD) Datenblatt: EPF8636A.pdf

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15 .00*
Altera
EPM3064ATC44-10N
CPLD - Complex Programmable Logic Operating Supply Voltage: 3.3 V Number of Macrocells: 64 Macrocell Number of I/Os: 34 I/O Supply Voltage - Max: 3.6 V Supply Voltage - Min: 3 V Maximum Operating Frequency: 222.2 MHz Propagation Delay - Max: 4.5 ns Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 70 C

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7 .07*
Altera
EPM570F256I5N
CPLD - Complex Programmable Logic Devices - Number of Macrocells: 440 - Number of Logic Array Blocks - LABs: 57 - Maximum Operating Frequency: 304 MHz - Propagation Delay - Max: 5.4 ns - Number of I/Os: 160 I/O - Operating Supply Voltage: 2.5 V, 3.3 V - Minimum Operating Temperature: - 40 C - Maximum Operating Temperature: + 85 C Datenblatt: EPM570.pdf

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20 .00*
Altera
EPM7032AELC44-7
High-Performance, EEPROM-Based Programmable Logic Devices Datenblatt: EPM7032A.pdf

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3 .00*
Altera
EPM7032LC44-15
Beschreibung: Programmable Logic Device Datenblatt: EPM7032.pdf

12 .00*
Altera
EPM7064LC44-10
Beschreibung: Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins Datenblatt: EPM7064.pdf

17 .50*
Altera
EPM7064LC44-15
CPLD - Complex Programmable Logic Number of Macrocells: 64 Number of Gates: 1250 Number of Logic Array Blocks - LABs: 4 Maximum Operating Frequency: 151.5 MHz Propagation Delay - Max: 6 ns Number of I/Os: 36 I/O Operating Supply Voltage: 5 V Supply Voltage - Max: 3.6 V Supply Voltage - Min: 3 V Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 70 C Datenblatt: EPM7064.pdf

10 .00*
Altera
EPM7064LC44-7
Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins Number of Macrocells: 64 Number of Gates: 1250 Number of Logic Array Blocks - LABs: 4 Maximum Operating Frequency: 151.5 MHz Propagation Delay - Max: 6 ns Number of I/Os: 36 I/O Operating Supply Voltage: 5 V Supply Voltage - Max: 3.6 V Supply Voltage - Min: 3 V Minimum Operating Temperature: 0 C Maximum Operating Temperature: + 70 C Datenblatt: EPM7064.pdf

17 .50*
Altera
EPM7064LC68-10
Beschreibung: Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins Datenblatt: EPM7064.pdf

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9 .00*
Altera
EPM7096LC68-15
Beschreibung: High Density, erasable CMOS EPLD Datenblatt: EPM7096.pdf

10 .00*
Altera
EPM7096LC68-2
Beschreibung: High Density, erasable CMOS EPLD Datenblatt: EPM7096.pdf

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7 .60*
Altera
EPM7096LC68-7
High Density, erasable CMOS EPLD - High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture - 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 - Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices - Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells - 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) - PCI-compliant devices available Datenblatt: EPM7096.pdf

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20 .00*
Altera
EPM7128AETC14410N

21 .00*
Altera
EPM7128ELC84-15
Beschreibung: Programmable Logic CPLD MAX7000 Family, 128 Macro Cells, 76.9MHz, 5V Datenblatt: EPM7128E.pdf

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30 .00*
Altera
EPM7128ELC84-7
Beschreibung: Programmable Logic CPLD MAX7000 Family, 128 Macro Cells, 76.9MHz, 5V Datenblatt: EPM7128E.pdf

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50 .00*
Altera
EPM7128SLC84-15
Beschreibung: Programmable Logic CPLD MAX7000 Family, 128 Macro Cells, 76.9MHz, 5V Datenblatt: EPM7128.pdf

20 .00*
Altera
EPM7128SLC84-15 RoHs
Beschreibung: Programmable Logic CPLD MAX7000 Family, 128 Macro Cells, 76.9MHz, 5V Datenblatt: EPM7128.pdf

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15 .00*
Altera
EPM7128STC100-15N
CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 Family Name: MAX® 7000S Program Memory Type: EEPROM Number of Logic Blocks/Elements: 8 Number of Global Clocks: 2 Number of Macro Cells: 128 Product Terms: 32 Device System Gates: 2500 Data Gate: No Maximum Number of User I/Os: 84 In-System Programmability: Yes Programmability: Yes Reprogrammability Support: Yes Maximum Internal Frequency (MHz): 100 Maximum Clock to Output Delay (ns): 8 Maximum Propagation Delay Time (ns): 15 Speed Grade: 15 Individual Output Enable Control: Yes Minimum Operating Supply Voltage (V): 4.75 Maximum Operating Supply Voltage (V): 5.25 Typical Operating Supply Voltage (V): 5 I/O Voltage (V): 3.3 / 5 Minimum Operating Temperature (°C): 0 Maximum Operating Temperature (°C): 70 Supplier Temperature Grade: Commercial Datenblatt: EPM7128S.pdf

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11 .00*