16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
- Effective Zero Wait-State Performance up to 33 MHz
- SmartVoltage Technology
- 0.33 MB/sec Write Transfer Rate
- Configurable x8 or x16 Operation
- 2 uA Typical Deep Power-Down
- 1 mA Typical Active ICC Current in Static Mode
Datenblatt:
E28F016XS.pdf
Industrial Motor Control Microcontroller
Operating Supply Voltage: 5.5 V
Data Bus Width: 16 bit
Maximum Clock Frequency: 16 MHz
Code Name: MCS96
Minimum Operating Temperature: - 40 C
Maximum Operating Temperature: + 85 C
Datenblatt:
EE80C196MC.pdf
Peripheral Interface Adaptateur (PIA)
- 8-Bit Bidirectional Data Bus for communication with the MPU
- Two Bidirectional 8-Bit Buses for Interface to Periphals
- Two Programmable Control Registers
- Two programmable Data Direction Registers
- Four Individualy-Controlled Interrupt Input Lines / Two Usable as Peripheral Control Outputs
- Handshake Control Logic for Input and Output Peripheral Operator
Datenblatt:
EF6821.pdf
Peripheral Interface Adaptateur (PIA)
- 8-Bit Bidirectional Data Bus for communication with the MPU
- Two Bidirectional 8-Bit Buses for Interface to Periphals
- Two Programmable Control Registers
- Two programmable Data Direction Registers
- Four Individualy-Controlled Interrupt Input Lines / Two Usable as Peripheral Control Outputs
- Handshake Control Logic for Input and Output Peripheral Operator
Datenblatt:
EF6821.pdf
Low Power Windowed Watchdog with Reset, Sleep Mode Functions
Low quiescent current 35 ?A
-40°C to +125°C temperature range
Windowed watchdog with an adjustable time windows, guaranteeing a minimum time and a maximum time
between software clearing of the watchdog
Time base accuracy ±8% (at 100ms)
Voltage reference accuracy ±3%
Sleep mode function (V55)
Adjustable threshold voltage using external resistors
Adjustable power on reset (POR) delay using one external resistor
Open-drain active-low RESET output
Reset output guaranteed for regulated output voltage down to 1.2 V
System ENABLE output offers added security
Qualified according to AEC-Q100
Operating junction temperature Tj: -40 to +125 °C
Supply voltage VDD: 1.2 to 5.5 V
RC-oscillator programming ROSC: 10 to 1000 kOhm
Datenblatt:
EM6151.pdf
CPLD - One-Time-Programmable Logic Device - 48 Macrocells
Program Memory Type: EPROM
Number of Global Clocks: 2
Number of Macro Cells: 48
Product Terms: 8
Device System Gates: 900
Data Gate: No
Maximum Number of User I/Os: 64
In-System Programmability: No
Programmability: Yes
Reprogrammability Support: Yes
Maximum Internal Frequency (MHz): 41.67
Maximum Clock to Output Delay (ns): 20
Maximum Propagation Delay Time (ns): 35
Speed Grade: 35
Individual Output Enable Control: No
Minimum Operating Supply Voltage (V): 4.75
Maximum Operating Supply Voltage (V): 5.25
Typical Operating Supply Voltage (V): 5
Minimum Operating Temperature (°C): 0
Maximum Operating Temperature (°C): 70
FPGA - Field Programmable Gate Array
Number of Logic Elements: 12060 LE
Number of I/Os: 249 I/O
Supply Voltage - Min: 1.5 V
Supply Voltage - Max: 3.3 V
Maximum Operating Frequency: 250 MHz
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Datenblatt:
EP1C12F324C8N.pdf
Programmable Logic Device ACEX 1K Family
- Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array block (EAB)
– Logic array for general logic functions
- High density
– 10,000 to 100,000 typical gates
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be used without reducing logic capacity
- Cost-efficient programmable architecture for high-volume applications
– Cost-optimized process
– Low cost solution for high-performance communications applications
- System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Datenblatt:
EP1K100QC208-3N.pdf
FPGA - Field Programmable Gate Array
Embedded Memory: 117 kbit
Number of I/Os: 89 I/O
otal Memory: 119808 bit
Maximum Operating Frequency: 260 MHz
Operating Supply Voltage: 1.15 V to 1.25 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C